Increasing demand for smaller, more compact, and increasingly complex electronics has driven manufacturers to adopt new technology. In the past decade, there has been wide acceptance of flip chip microelectronic assembly as an integrated circuit package solution. The flip chips are active electronic components offering an extensive ability to incorporate numerous features and capabilities. The assemblies typically include one or more electronic components surface-mounted to a substrate, such as a printed circuit board (PCB). The substrate is used to mechanically support and electrically connect the electronic component using conductive pathways, tracks or signal traces etched from copper sheets laminated onto the non-conductive substrate.
One such surface mount method of inter-connecting the electrical component to the substrate is known as solder bump or ball technology. This interconnection typically makes these circuits superior in performance to other more conventional interconnection technologies. It also facilitates cheap and speedy high-volume production; the production and soldering of PCBs can be done by totally automated equipment. However, significant manufacturing problems exist with the integrity of the connection between the electronic component and the substrate onto which the components are connected.
For the interconnection, a plurality of terminals, such as input/output terminals, is arranged in a pattern on the surface of the electronic component and the electronic component is placed face down and bonded to the substrate. Each terminal must connect properly with the corresponding solder bump on the substrate. These bump terminals are spherical terminals formed on the surface of the substrate; they include metal bumps formed with a plating method and solder bumps formed with a solder dip method. Consequently, it is necessary that the form and height of the bumps be uniform. A height less than other bumps will cause the connection with the electrode on the substrate to be no good. When the height of the bumps is uneven, there is an increased risk of a short circuit between adjacent bumps.
Generally, each electronic component may be provided with numerous bumps, in which case visual inspection of the bumps on each integrated circuit assembly is almost impossible. Nevertheless, it is necessary to find any defects of the bumps onto which the electronic component is mounted. Therefore, various bump inspection techniques have been proposed for automated nondestructive inspection of the solder joint quality of the solder bumps connecting the electronic components. These include x-ray detection methods, acoustic microscopy, and functional testing methods. There are two main types of x-ray detection methods: laminography and microfocus radiography. Acoustic microscopes utilize high-frequency ultrasound to examine the internal features in materials and components. Defects such as preexisting voids or non-wet conditions can be observed. The most widely used on-line inspection techniques are functional testing methods, such as the flying probe or the bed of nails methods. In these techniques, a test fixture checks for electrical continuity and proper operation of the circuit assembly by comparing the electrical response at specific nodes of the assembly to previously determined values. However, unsoldered joints may still pass this test if mechanical contact exists, even though the joint may fail after a short service life because of cracks or partial connections.
These inspection methods also have other drawbacks. The technologies utilized in inspecting the joint defects typically require individual inspection of each bump-terminal connection, which can be time and resource consuming. Moreover, because some of the bump defects typically emerge subsequent to the reflow process, the conventional bump inspection techniques are likely to be misleading since the bump dimensions are generally measured prior to the reflow process.
Other techniques for post-bond inspection such as that disclosed in the Wang et al., US 2011/0051124 publication have generally focused on the alignment of the electronic component relative to the substrate onto which the electronic component is placed. However, even with proper alignment, the electrical connections between the electronic component and substrate bumps may still have defects that would be undiscovered if relying on the alignment data.
Accordingly, there remains a need for a method and apparatus that can provide reliable detection of a defect in a connection between a substrate and an electronic component mounted thereon.